Perancangan Sistem Digital

Minggu 1: Peta Karnaugh

Minggu 2: Intro VHDL

Intro VHDL (2)

Flip flop

counter

Hazard Protection

UTS

Setelah UTS:
slide MealyMoore.ppt
slide MealyMoore.ppt
bab7-Memory.pdf

Leave a Reply

Fill in your details below or click an icon to log in:

WordPress.com Logo

You are commenting using your WordPress.com account. Log Out / Change )

Twitter picture

You are commenting using your Twitter account. Log Out / Change )

Facebook photo

You are commenting using your Facebook account. Log Out / Change )

Google+ photo

You are commenting using your Google+ account. Log Out / Change )

Connecting to %s


%d bloggers like this: